Semiconductor memory devices for storing data can typically be categorized as either volatile memory devices or non-volatile memory devices. The volatile memory devices lose their stored data when their power supplies are interrupted, however the non-volatile memory devices retain their stored data even when their power supplies are interrupted. Thus, the non-volatile memory devices are widely used in memory cards, mobile telecommunication systems and the like.
Programming and erasing operations of the non-volatile memory devices can be achieved by the F-N (Fowler-Nordheim) tunneling effect through a tunnel oxide layer interposed between a floating gate and a substrate. The F-N tunneling occurs when an electric field of 6 MV/cm to 8 MV/cm is applied to the tunnel oxide layer. The electric field between the floating gate and the substrate is actually induced by applying a high voltage of 15 volts to 20 volts to a control gate electrode, which is located over the floating gate. Accordingly, it is necessary to increase the so-called coupling ratio of the non-volatile memory cell in order to reduce the programming voltage or the erasing voltage. The coupling ratio (CR) is given by the following equation.CR=Cono/(Cono+Ctun)
wherein, “Cono” represents inter-gate dielectric capacitance between the floating gate and the control gate electrode, and “Ctun” represents tunnel oxide capacitance between the floating gate and the substrate.
As can be seen from the above equation, it is necessary to increase the inter-gate dielectric capacitance Cono and/or to reduce the tunnel oxide capacitance Ctun in order to obtain a higher coupling ratio. Accordingly, an oxide-nitride-oxide (ONO) layer is widely used as the inter-gate dielectric layer in order to increase the coupling ratio. However, in the event that the inter-gate dielectric layer is formed of the ONO layer, oxygen atoms can be continuously introduced into the interface between the nitride layer of the ONO layer and a top or a bottom oxide layer of the ONO layer during subsequent processes. Thus, the ONO layer becomes thicker and the coupling ratio is undesirably reduced.
FIG. 1 is a typical top plan view showing a portion of a cell array region of the nonvolatile memory device.
Referring to FIG. 1, isolation layers 12 (or 52) are disposed at predetermined regions of a semiconductor substrate to define an active region. At least one control gate electrode 26 (or 66) runs across the isolation layers 12 (or 52) and the active region therebetween. A floating gate 24 (or 64) is interposed between the control gate electrode 26 (or 66) and the active region. The floating gate 24 (or 64) is electrically insulated from the substrate by a tunnel oxide layer (not shown). Also, the floating gate 24 (or 64) is electrically insulated from the control gate electrode 26 (or 66) by an inter-gate dielectric layer (not shown). Accordingly, charges are stored in the floating gate that acts as a storage node.
FIGS. 2A and 3A are cross-sectional views for illustrating a conventional method of fabricating a non-volatile memory device, taken along the line I-I′ of FIG. 1. FIGS. 2B and 3B are cross-sectional views for illustrating a conventional method of fabricating a non-volatile memory device, taken along the line II-II′ of FIG. 1.
Referring to FIGS. 2A and 2B, isolation layers 52 are formed at a semiconductor substrate 10 to define an active region and a stacked gate 70 is formed on the substrate having the isolation layers 52. The stacked gate 70 comprises a floating gate 64, an inter-gate dielectric layer 60 and a control gate electrode 66, which are sequentially stacked. In addition, a tunnel oxide layer 54 is formed between the stacked gate 70 and the active region.
The method of forming the stacked gate 70 includes forming a floating gate pattern that covers the active region. The inter-gate dielectric layer 60 is then formed on the entire surface of the substrate having the floating gate pattern. The inter-gate dielectric layer 60 is formed by sequentially stacking a bottom dielectric layer 57, an intermediate dielectric layer 58 and a top dielectric layer 59. The bottom dielectric layer 57 and the top dielectric layer 59 are formed of a CVD oxide layer, and the intermediate dielectric layer 58 is formed of a silicon nitride layer. A control gate conductive layer is then formed on the inter-gate dielectric layer 60. The control gate conductive layer, the inter-gate dielectric layer 60 and the floating gate pattern are successively etched to form the stacked gate 70. Undesirably, etch damage occurs on the semiconductor substrate 10.
Referring to FIGS. 3A and 3B, a thermal oxidation process is applied to the substrate having the stacked gate 70 in order to cure the etch damage. As a result, the surface of the semiconductor substrate 10 between the adjacent stacked gates 70, and the sidewalls and top surfaces of the stacked gates 70 are oxidized to form a thermal oxide layer 68. At this time, the edges of the inter-gate dielectric layer 60 and the tunnel oxide layer 64 become thicker, as shown in FIG. 3B. In particular, the edges of the inter-gate dielectric layer 60 become thicker as compared to the tunnel oxide layer. This is because the diffusibility of the oxygen atoms into the inter-gate dielectric layer 60 is higher than that into the tunnel oxide layer.
In more detail, the oxygen atoms are diffused along the interfaces among the semiconductor substrate 10, the tunnel oxide layer 54, the floating gate 64, the bottom oxide layer 57, the intermediate nitride layer 58, the top oxide layer 59 and the control gate electrode layer 66 during the thermal oxidation process. Thus, the edges of the floating gate 64 and the control gate electrode 66 are oxidized to form bird's beaks. As a result, the edges of the inter-gate dielectric layer 60 and the tunnel oxide layer 54 become thicker.
In particular, the edge thickness of the inter-gate dielectric layer 60 becomes more increased as compared to that of the tunnel oxide layer 54. This is because the intermediate nitride layer 58 is formed of a silicon nitride layer having an oxidation-resistant characteristic. In other words, the sidewall of the intermediate nitride layer 58 is not oxidized even though the thermal oxidation process is performed. Therefore, the sidewall of the intermediate nitride layer 58 is still exposed, whereas the interface between the tunnel oxide layer 54 and the floating gate 64 is covered with the thermal oxide layer 68. Consequently, the oxygen atoms can be continuously supplied into the edge (B) of the intermediate dielectric layer 58, i.e., the interfaces between the intermediate dielectric layer 58 and the top oxide layer 59 as well as between the intermediate dielectric layer 58 and the bottom oxide layer 57, during the thermal oxidation process. Accordingly, the edge thickness of the inter-gate dielectric layer 60 becomes more increased as compared to that of the tunnel oxide layer 54.
According to the prior art as described above, the thickness of the inter-gate dielectric layer becomes more increased as compared to the tunnel oxide layer. Thus, the coupling ratio of the non-volatile memory cell is reduced. Also, the thickness deviations of the tunnel oxide layer and the inter-gate dielectric layer are increased. This leads to non-uniform characteristics of the memory cells throughout the semiconductor substrate.